HMC704LP4E【PDF 11/44 页】IC FRACT-N PLL 16BIT 24QFN

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Sheet目录1996

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5 - 19

HMC704LP4E

v03.1211

8 GHz fractionaL-n PLL

For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

ref Path ’r’ Divider

The reference path “R” divider is based on a 14 bit counter and can divide input signals of up to 350MHz input by values

from 1 to 16,383 and is controlled by “Reg 02h”[13:0]. The reference divider output may be viewed in test mode on the

LD_sDO pin, by setting “Reg 0Fh”[4:0] = 9d.

rf Path

The RF path is shown in Figure 28. This path features a low noise 8GHz RF input buffer followed by an 8GHz RF divide-

by-2 with a selectable bypass. If the VCO input is below 4GHz the RF divide-by-2 should be by-passed for reduced

power consumption and improved performance in fractional mode. The RF divide-by-2 is followed by the N divider, a 19

bit divider that can operate in either integer or fractional mode with up to 4GHz inputs. Finally the N divider is followed by

the Phase Detector (PD), which has two inputs, the RF path from the VCO (V) and the reference path (R) from the crys-

tal. The PD can operate at speeds up to 80MHz in fractional Mode A, 100MHz in fractional Mode B and 115MHz in inte-

ger mode.

rf input Stage

The RF input stage provides the path from the external VCO to the phase detector via the RF or ’N’ divider. The RF in-

put path is rated to operate up to 8GHz across all conditions. The RF input stage is a differential common emitter stage

with internal DC bias, and is protected by EsD diodes as shown in Figure 29. This input is not matched to 50 Ohms. A

50 Ohm resistor placed across the inputs can be used if desired. In most applications the input is used single-ended

into either the VCOIP or VCOIN pin with the other input connected to ground through a DC blocking capacitor. The

preferred input level for best spectral performance is -10dBm nominally.

Figure 29. RF Input Stage

Figure 28. RF Path

RF Buffer

/2 or

8GHz

4GHz

Bypass

19 Bit /N

80MHz/100MHz Fractional

115MHz Integer

Ref Path

sEL

CONTROL

VCOIP

VCOIN

RF Divide by 2 N Divider

Phase Detector

VPPCP

Charge Pump

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